Lc-3 manual

LC-3 Simulator Manual Get the latest version of the simulator here. Date: 2 September Overview This document describes the Java version of the LC-3 Simulator (and assembler) developed at the University of Pennsylvania. It does not teach LC-3 programming or debugging techniques. LC-3 has three condition code registers: N -- negative Z -- zero P -- positive (greater than zero) Set by any instruction that writes a value to a register (ADD, AND, NOT, LD, LDR, LDI, LEA) Exactly one will be set at all times Based on the last instruction that altered a register. The Instruction Set Architecture (ISA) of the LC-3 is defined as follows: Memory address space 16 bits, corresponding to locations, each containing one word (16 bits). Addresses are numbered from 0 (i.e, x) to 65, (i.e., xFFFF). Addresses are used to identify memory locations and memory-mapped I/O device registers. Certain regions of memory are.

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LC-3 Simulator Manual Get the latest version of the simulator here. Date: 2 September Overview This document describes the Java version of the LC-3 Simulator (and assembler) developed at the University of Pennsylvania. It does not teach LC-3 programming or debugging techniques. 3 R1 3 LC-3 Instruction Encoding: Example 1 R1 3 2 1 0 R1 3 CIT 11 Using Operate Instructions: OR How do we OR two values? Goal R1 <- R2 OR R3 (No such instruction) Idea (Use DeMorgan’s Law). LC-3 Instruction Encoding: Example 3 1. We write an instruction that will store contents from R2 into memory at location x 2. This instruction will be placed in memory at location x M[] 3 2 1 0 CIT 26 Indirect Addressing Mode Another way to produce full bit address.